From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Oct 2018 15:12:31 +0000 (+0100)
Subject: simplify sv_proc_t redirection of RS1-3 / FRS1 macrhos
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe6089354c26e625c8c449bdaa5fb82c99c21048;p=riscv-isa-sim.git

simplify sv_proc_t redirection of RS1-3 / FRS1 macrhos
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 616ed33..f0759bc 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -3,7 +3,7 @@
 
 void (sv_proc_t::WRITE_RD)(reg_t value)
 {
-    WRITE_RD( value );
+    WRITE_REG( insn->rd(), value );
 }
 
 /*
@@ -13,11 +13,18 @@ reg_t (sv_proc_t::READ_REG)(uint64_t i)
 }
 */
 
-RS1::operator reg_t () const & {
-    return _insn->p->get_state()->XPR[_insn->rs1()];
+reg_t sv_proc_t::get_rs1()
+{
+    return insn->p->get_state()->XPR[insn->rs1()];
 }
 
-RS2::operator reg_t () const & {
-    return _insn->p->get_state()->XPR[_insn->rs2()];
+reg_t sv_proc_t::get_rs2()
+{
+    return insn->p->get_state()->XPR[insn->rs2()];
+}
+
+freg_t sv_proc_t::get_frs1()
+{
+    return READ_FREG(insn->rs1());
 }
 
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 2efcce3..cb4848a 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -7,19 +7,27 @@
 
 #undef RS1
 #undef RS2
+#undef FRS1
 
 class processor_t;
 class insn_t;
 
-class RS1 {
+/*
+class FRS1 {
     public:
         sv_insn_t *_insn;
-        RS1() : _insn(NULL) {}
+        FRS1() : _insn(NULL) {}
         //sv_insn_t & operator = (sv_insn_t &i)
         //{ _insn = &i; return i; }
-        operator reg_t () const &;
+        operator freg_t () const &;
 };
+*/
+
+#define FRS1 get_frs1()
+#define RS1 get_rs1()
+#define RS2 get_rs2()
 
+/*
 class RS2 {
     public:
         sv_insn_t *_insn;
@@ -28,34 +36,27 @@ class RS2 {
         //{ _insn = &i; return i; }
         operator reg_t () const &;
 };
+*/
 
 class sv_proc_t
 {
 public:
-    sv_proc_t(processor_t *_p) : p(_p) {}
+    sv_proc_t(processor_t *_p) : p(_p), insn(NULL) {}
     void (WRITE_RD)(reg_t value);
     //reg_t (READ_REG)(uint64_t i);
 
     processor_t *p;
-
-    class RS1 RS1;
-    class RS2 RS2;
-
-    class {
-        public:
-        sv_insn_t *_insn;
-        sv_insn_t & operator = (sv_insn_t &i)
-        { _insn = &i; return i; }
-        operator sv_insn_t () const & { return *_insn; }
-        uint64_t rd() { return _insn->rd(); }
-    } insn;
+    sv_insn_t *insn;
 
     void set_insn(sv_insn_t *i) {
-        this->insn = *i;
-        RS1._insn = i;
-        RS2._insn = i;
+        this->insn = i;
     }
 
+    reg_t get_rs1();
+    reg_t get_rs2();
+
+    freg_t get_frs1();
+
 #include "sv_insn_decl.h"
 };