From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sat, 17 Sep 2022 16:17:33 +0000 (+0300)
Subject: power_insn: support saturation mode
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe6290a5d83c41ed3d6db502ca02a9dd6a5c2d40;p=openpower-isa.git

power_insn: support saturation mode
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index eb04abad..769847f0 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1348,6 +1348,10 @@ class NormalRM(BaseRM):
                 yield f"dz"
             if self.sz:
                 yield f"sz"
+            if self.sat:
+                yield "sats"
+            else:
+                yield "satu"
             yield from super().specifiers
 
     class satx(BaseRM):
@@ -1363,6 +1367,10 @@ class NormalRM(BaseRM):
                 yield f"dz"
             if self.sz:
                 yield f"sz"
+            if self.sat:
+                yield "sats"
+            else:
+                yield "satu"
             yield from super().specifiers
 
     class satpu(BaseRM):
@@ -1378,6 +1386,10 @@ class NormalRM(BaseRM):
                 yield f"dz"
             if self.sz:
                 yield f"sz"
+            if self.sat:
+                yield "sats"
+            else:
+                yield "satu"
             yield from super().specifiers
 
     class prrc1(BaseRM):
@@ -1469,6 +1481,10 @@ class LDSTImmRM(BaseRM):
                 yield f"dz"
             if self.sz:
                 yield f"sz"
+            if self.sat:
+                yield "sats"
+            else:
+                yield "satu"
             yield from super().specifiers
 
     class prrc1(BaseRM):
@@ -1531,6 +1547,10 @@ class LDSTIdxRM(BaseRM):
                 yield f"dz"
             if self.sz:
                 yield f"sz"
+            if self.sat:
+                yield "sats"
+            else:
+                yield "satu"
             yield from super().specifiers
 
     class prrc1(BaseRM):