From: lkcl Date: Fri, 12 Aug 2022 13:59:57 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~878 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe656f900cea0a68eff4f73d44fb6356cff2e246;p=libreriscv.git --- diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index 44b70792d..b8a862bab 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -614,7 +614,7 @@ Pack/Unpack has to be deployed across SVP64 sparingly (not so uniformly general) due to the fact that it takes up two RM.EXTRA bits, putting pressure on developers by restricting the register range as above. -# LD/ST with zero-immediate +# LD/ST with zero-immediate vs mapreduce mode LD/ST operations with a zero immediate effectively means that on a Vector operation the element index to offset the memory location is @@ -626,7 +626,7 @@ that Power ISA has cache-inhibited LD/STs, for accessing memory-mapped peripherals and other crucial uses. Thus, *despite not being a mapreduce mode*, zero-immediates cause multiple hits on the same element. -Recall above that mapreduce mode is not actually mapreduce at all: it is +Mapreduce mode is not actually mapreduce at all: it is a relaxation of the normal rule where if the destination is a Scalar the Vector for-looping is not terminated on first write to the destination. Instead, the developer is expected to exploit the strict Program Order,