From: Palmer Dabbelt <palmer@dabbelt.com>
Date: Wed, 19 Apr 2017 23:59:10 +0000 (-0700)
Subject: Have ndmreset reset the processor
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe678ee09925b90058ff80c037341b873e6da429;p=riscv-isa-sim.git

Have ndmreset reset the processor
---

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 533b959..5f66ebe 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -437,6 +437,9 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value)
               debug_rom_flags[dmcontrol.hartsel] |= (1 << DEBUG_ROM_FLAG_RESUME);
               resumeack[dmcontrol.hartsel] = false;
             }
+	    if (dmcontrol.ndmreset) {
+	      proc->reset();
+	    }
           }
         }
         return true;