From: Sebastien Bourdeauducq Date: Thu, 9 May 2013 08:51:50 +0000 (+0200) Subject: dvisampler/dma: reverse slot allocation order X-Git-Tag: 24jan2021_ls180~2940 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe87221d2b4da14ba7a99e27aed80d1bbbe8f715;p=litex.git dvisampler/dma: reverse slot allocation order --- diff --git a/milkymist/dvisampler/dma.py b/milkymist/dvisampler/dma.py index 4bded615..0013bc18 100644 --- a/milkymist/dvisampler/dma.py +++ b/milkymist/dvisampler/dma.py @@ -46,7 +46,7 @@ class _SlotArray(Module, AutoCSR): change_slot = Signal() current_slot = Signal(max=nslots) - self.sync += If(change_slot, [If(slot.address_valid, current_slot.eq(n)) for n, slot in enumerate(slots)]) + self.sync += If(change_slot, [If(slot.address_valid, current_slot.eq(n)) for n, slot in reversed(list(enumerate(slots)))]) self.comb += change_slot.eq(~self.address_valid | self.address_done) self.comb += [