From: lkcl <lkcl@web>
Date: Mon, 9 May 2022 17:33:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2286
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe8836ccd5d908ce423b9c81e3401020496b6f55;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index f8ebbf29d..25f8e6dee 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -916,6 +916,10 @@ and how that helps Register Hazards and SIMD amortisation
 on a GB-OoO Micro-architecture)
 </blockquote>*
 
+Draft Image:
+
+<img src="/openpower/sv/zolc svp64 extrav.jpg" width=800 />
+
 **Use-case variant: More powerful in-memory PEs**
 
 An obvious variant of the above is that, if there is inherently