From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 9 Jun 2020 17:53:35 +0000 (+0100)
Subject: rename truncaddr to splitaddr, return LSBs and MSBs
X-Git-Tag: div_pipeline~444
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe9ceed7f2dfc35383abf8c8326c894c4f9f77ea;p=soc.git

rename truncaddr to splitaddr, return LSBs and MSBs
---

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 919d39be..b0c9ca82 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -330,10 +330,10 @@ class L0CacheBuffer(Elaboratable):
     def addrbits(self):
         return log2_int(self.mem.regwid//8)
 
-    def truncaddr(self, addr):
-        """truncates the address to the top bits of the memory granularity
+    def splitaddr(self, addr):
+        """split the address into top and bottom bits of the memory granularity
         """
-        return addr[self.addrbits:]
+        return addr[:self.addrbits], addr[self.addrbits:]
 
     def elaborate(self, platform):
         m = Module()