From: whitequark <cz@m-labs.hk>
Date: Mon, 24 Dec 2018 01:38:32 +0000 (+0000)
Subject: back.rtlil: always output negative values as two's complement.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe9d773e253b3cd32d97b7ce9a74be46beb2d991;p=nmigen.git

back.rtlil: always output negative values as two's complement.

- is valid in RTLIL but means something entirely different.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 0bd5f08..91bd1c1 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -361,7 +361,8 @@ class _RHSValueCompiler(_ValueCompiler):
         if isinstance(value.value, str):
             return "{}'{}".format(value.nbits, value.value)
         else:
-            return "{}'{:0{}b}".format(value.nbits, value.value, value.nbits)
+            value_twos_compl = value.value & ((1 << value.nbits) - 1)
+            return "{}'{:0{}b}".format(value.nbits, value_twos_compl, value.nbits)
 
     def on_Signal(self, value):
         wire_curr, wire_next = self.s.resolve(value)