From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Sep 2019 07:01:31 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xc7dsp
X-Git-Tag: working-ls180~1039^2~138
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=feb3fa65a3267acda76b7b6eea0e9ffedb281b85;p=yosys.git

Merge remote-tracking branch 'origin/master' into xc7dsp
---

feb3fa65a3267acda76b7b6eea0e9ffedb281b85
diff --cc CHANGELOG
index f0a0d0fae,e416d152c..50c611b8d
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -38,11 -38,7 +38,12 @@@ Yosys 0.9 .. Yosys 0.9-de
      - Improvements in pmgen: slices, choices, define, generate
      - Added "xilinx_srl" for Xilinx shift register extraction
      - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
+     - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
 +    - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
 +    - Added "xilinx_dsp" for Xilinx DSP packing
 +    - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
 +    - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
 +    - "synth_ice40 -dsp" to infer DSP blocks
  
  Yosys 0.8 .. Yosys 0.9
  ----------------------
diff --cc techlibs/xilinx/Makefile.inc
index 2cf0e8e33,b5e81a79d..5f5aa5518
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@@ -35,10 -35,10 +35,11 @@@ $(eval $(call add_share_file,share/xili
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt))
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
- $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
+ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_ff_map.v))
+ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_ff_map.v))
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
 +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/dsp_map.v))
  
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_map.v))
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_unmap.v))