From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 14 Oct 2018 05:16:03 +0000 (+0100)
Subject: add rv_sr
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fec3b3e7777128070188387f5e645ee27a351f50;p=riscv-isa-sim.git

add rv_sr
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 30619dd..a986cef 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -287,3 +287,13 @@ sreg_t sv_proc_t::rv_lt(sreg_t lhs, sreg_t rhs)
     return lhs < rhs;
 }
 
+reg_t sv_proc_t::rv_gt(reg_t lhs, reg_t rhs)
+{
+    return lhs > rhs;
+}
+
+sreg_t sv_proc_t::rv_gt(sreg_t lhs, sreg_t rhs)
+{
+    return lhs > rhs;
+}
+