From: Bernd Edlinger Date: Fri, 1 Jan 2016 18:45:41 +0000 (+0000) Subject: re PR target/68917 (test suite failure for builtin-bitops-1.c) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fecd16d2387f1f1b0f376aba290171c880897ab0;p=gcc.git re PR target/68917 (test suite failure for builtin-bitops-1.c) PR target/68917 * config/tilegx/tilegx.md (clzsi2): Don't create DI subregs of SI values. Explicitly convert SI to DI and vice-versa. From-SVN: r232028 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7d27a834130..8b1fd2d3536 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-01-01 Bernd Edlinger + + PR target/68917 + * config/tilegx/tilegx.md (clzsi2): Don't create DI subregs of + SI values. Explicitly convert SI to DI and vice-versa. + 2016-01-01 Jakub Jelinek PR tree-optimization/69070 diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md index 944953c34b2..a2c1aef3975 100644 --- a/gcc/config/tilegx/tilegx.md +++ b/gcc/config/tilegx/tilegx.md @@ -1799,13 +1799,16 @@ (define_expand "clzsi2" [(set (match_dup 2) - (ashift:DI (match_operand:SI 1 "reg_or_0_operand" "") + (zero_extend:DI (match_operand:SI 1 "reg_or_0_operand" ""))) + (set (match_dup 2) + (ashift:DI (match_dup 2) (const_int 32))) - (set (subreg:DI (match_operand:SI 0 "register_operand" "") 0) - (clz:DI (match_dup 2)))] + (set (match_dup 2) + (clz:DI (match_dup 2))) + (set (match_operand:SI 0 "register_operand" "") + (subreg:SI (match_dup 2) 0))] "" { - operands[1] = simplify_gen_subreg (DImode, operands[1], SImode, 0); operands[2] = gen_reg_rtx (DImode); })