From: Yunsup Lee Date: Mon, 4 Apr 2011 08:50:56 +0000 (-0700) Subject: [opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fed0e53ae71379f3d9cbe31998c72b20e60f332e;p=riscv-isa-sim.git [opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.) --- diff --git a/riscv/execute.h b/riscv/execute.h index c9c17a0..5ee33c7 100644 --- a/riscv/execute.h +++ b/riscv/execute.h @@ -1253,6 +1253,58 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/jal.h" break; } + case 0x73: + { + switch((insn.bits >> 0x7) & 0x7) + { + case 0x0: + { + #include "insns/vcfgivl.h" + break; + } + case 0x1: + { + if((insn.bits & 0x3fffff) == 0xf3) + { + #include "insns/setvl.h" + break; + } + #include "insns/unimp.h" + } + case 0x2: + { + if((insn.bits & 0xffc003ff) == 0x173) + { + #include "insns/vf.h" + break; + } + #include "insns/unimp.h" + } + case 0x3: + { + if((insn.bits & 0x3fffff) == 0x1f3) + { + #include "insns/mov_vv.h" + break; + } + #include "insns/unimp.h" + } + case 0x4: + { + if((insn.bits & 0x3fffff) == 0x273) + { + #include "insns/fmov_vv.h" + break; + } + #include "insns/unimp.h" + } + default: + { + #include "insns/unimp.h" + } + } + break; + } case 0x77: { switch((insn.bits >> 0x7) & 0x7) diff --git a/riscv/insns/fmov_vv.h b/riscv/insns/fmov_vv.h new file mode 100644 index 0000000..e69de29 diff --git a/riscv/insns/mov_vv.h b/riscv/insns/mov_vv.h new file mode 100644 index 0000000..e69de29 diff --git a/riscv/insns/setvl.h b/riscv/insns/setvl.h new file mode 100644 index 0000000..e69de29 diff --git a/riscv/insns/vcfgivl.h b/riscv/insns/vcfgivl.h new file mode 100644 index 0000000..e69de29 diff --git a/riscv/insns/vf.h b/riscv/insns/vf.h new file mode 100644 index 0000000..e69de29