From: Connor Abbott <cwabbott0@gmail.com>
Date: Wed, 18 Sep 2019 17:47:28 +0000 (+0700)
Subject: lima/gpir: Fix 64-bit shift in scheduler spilling
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fed5b605f09ac1a6c23d2aeced7f9abccdf02139;p=mesa.git

lima/gpir: Fix 64-bit shift in scheduler spilling

There are 64 physical registers so the shift must be 64 bits.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
---

diff --git a/src/gallium/drivers/lima/ir/gp/scheduler.c b/src/gallium/drivers/lima/ir/gp/scheduler.c
index e069079591c..bf8bd63e57c 100644
--- a/src/gallium/drivers/lima/ir/gp/scheduler.c
+++ b/src/gallium/drivers/lima/ir/gp/scheduler.c
@@ -861,12 +861,12 @@ static uint64_t get_available_regs(sched_ctx *ctx, gpir_node *node,
          if (instr->reg0_use_count == 0)
             use_available = ~0ull;
          else if (!instr->reg0_is_attr)
-            use_available = 0xf << (4 * instr->reg0_index);
+            use_available = 0xfull << (4 * instr->reg0_index);
 
          if (instr->reg1_use_count == 0)
             use_available = ~0ull;
          else
-            use_available |= 0xf << (4 * instr->reg1_index);
+            use_available |= 0xfull << (4 * instr->reg1_index);
 
          available &= use_available;
       }