From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 4 Apr 2022 16:11:46 +0000 (+0100)
Subject: disable ethmac for now, pass firmware.hex to cypress qspi model
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fee8396c3535e614c2527ef49047ff1cc2157ac0;p=ls2.git

disable ethmac for now, pass firmware.hex to cypress qspi model
---

diff --git a/coldboot/Makefile b/coldboot/Makefile
index b1bd8de..8262c9c 100644
--- a/coldboot/Makefile
+++ b/coldboot/Makefile
@@ -16,6 +16,7 @@ SHORT_TIMER_MULT = 100
 # but remember to recompile external_core_top.v with a matching
 # --pc_reset=0xNNNNNNNN
 BOOT_INIT_BASE ?= 0x10000000
+# BOOT_INIT_BASE ?= 0x0
 
 LIBGRAMDIR = ../libgram
 LIBGRAMINC = ../libgram/include
diff --git a/runsimsoc_hyperram.sh b/runsimsoc_hyperram.sh
index 5972377..934c743 100755
--- a/runsimsoc_hyperram.sh
+++ b/runsimsoc_hyperram.sh
@@ -7,11 +7,16 @@ HYPERRAM_DIR=./hyperram_model/s27kl0641/model
 
 QSPI_DIR=./qspi_model/Cy15b104qs/model/
 
+FIRMWARE=./coldboot/coldboot.bin
+
+# convert firmware to 32-bit hex
+python3 scripts/bin2hex.py ${FIRMWARE} 32 > ${QSPI_DIR}/firmware.hex
+
 # create the build_simsoc/top.il file with firmware baked-in
-python3 src/ls2.py isim ./coldboot/coldboot.bin
+#python3 src/ls2.py isim ./coldboot/coldboot.bin
 
 # do some voodoo magic to get icarus to be happy with the ilang file
-yosys simsoc.ys
+#yosys simsoc.ys
 
 # fix a bug in Lattice ECP5 models
 cp ${LIB_DIR}/DDRDLLA.v DDRDLLA.v
@@ -34,6 +39,7 @@ iverilog -Wall -g2012 -s simsoc_hyperram_tb -o simsoc \
     ${LIB_DIR}/ODDRX2DQSB.v ${LIB_DIR}/IDDRX2DQA.v \
     DDRDLLA.v \
         -I ${QSPI_DIR} -DN25Q128A13E \
+        -Dmem_file_name=firmware.hex \
     ${QSPI_DIR}/cy15b104qs.v \
 	${LIB_DIR}/CLKDIVF.v
 vvp -n simsoc -fst-speed
diff --git a/simsoc.ys b/simsoc.ys
index 77d3d6d..e5e237a 100644
--- a/simsoc.ys
+++ b/simsoc.ys
@@ -18,34 +18,34 @@ read_verilog  ../uart16550/rtl/verilog/uart_tfifo.v
 read_verilog  ../uart16550/rtl/verilog/uart_wb.v
 read_verilog  ../tercel-qspi/tercel/phy.v 
 read_verilog  ../tercel-qspi/tercel/wishbone_spi_master.v
-read_verilog  ../ethmac/rtl/verilog
-read_verilog  ../ethmac/rtl/verilog/eth_clockgen.v
-read_verilog  ../ethmac/rtl/verilog/eth_cop.v
-read_verilog  ../ethmac/rtl/verilog/eth_crc.v
-read_verilog  ../ethmac/rtl/verilog/eth_fifo.v
-read_verilog  ../ethmac/rtl/verilog/eth_maccontrol.v
-read_verilog  ../ethmac/rtl/verilog/ethmac_defines.v
-read_verilog  ../ethmac/rtl/verilog/eth_macstatus.v
-read_verilog  ../ethmac/rtl/verilog/ethmac.v
-read_verilog  ../ethmac/rtl/verilog/eth_miim.v
-read_verilog  ../ethmac/rtl/verilog/eth_outputcontrol.v
-read_verilog  ../ethmac/rtl/verilog/eth_random.v
-read_verilog  ../ethmac/rtl/verilog/eth_receivecontrol.v
-read_verilog  ../ethmac/rtl/verilog/eth_registers.v
-read_verilog  ../ethmac/rtl/verilog/eth_register.v
-read_verilog  ../ethmac/rtl/verilog/eth_rxaddrcheck.v
-read_verilog  ../ethmac/rtl/verilog/eth_rxcounters.v
-read_verilog  ../ethmac/rtl/verilog/eth_rxethmac.v
-read_verilog  ../ethmac/rtl/verilog/eth_rxstatem.v
-read_verilog  ../ethmac/rtl/verilog/eth_shiftreg.v
-read_verilog  ../ethmac/rtl/verilog/eth_spram_256x32.v
-read_verilog  ../ethmac/rtl/verilog/eth_top.v
-read_verilog  ../ethmac/rtl/verilog/eth_transmitcontrol.v
-read_verilog  ../ethmac/rtl/verilog/eth_txcounters.v
-read_verilog  ../ethmac/rtl/verilog/eth_txethmac.v
-read_verilog  ../ethmac/rtl/verilog/eth_txstatem.v
-read_verilog  ../ethmac/rtl/verilog/eth_wishbone.v
-read_verilog  ../ethmac/rtl/verilog/timescale.v
+# errors in the ethmac rtl, comment out for now
+#read_verilog  ../ethmac/rtl/verilog/eth_clockgen.v
+#read_verilog  ../ethmac/rtl/verilog/eth_cop.v
+#read_verilog  ../ethmac/rtl/verilog/eth_crc.v
+#read_verilog  ../ethmac/rtl/verilog/eth_fifo.v
+#read_verilog  ../ethmac/rtl/verilog/eth_maccontrol.v
+#read_verilog  ../ethmac/rtl/verilog/ethmac_defines.v
+#read_verilog  ../ethmac/rtl/verilog/eth_macstatus.v
+#read_verilog  ../ethmac/rtl/verilog/ethmac.v
+#read_verilog  ../ethmac/rtl/verilog/eth_miim.v
+#read_verilog  ../ethmac/rtl/verilog/eth_outputcontrol.v
+#read_verilog  ../ethmac/rtl/verilog/eth_random.v
+#read_verilog  ../ethmac/rtl/verilog/eth_receivecontrol.v
+#read_verilog  ../ethmac/rtl/verilog/eth_registers.v
+#read_verilog  ../ethmac/rtl/verilog/eth_register.v
+#read_verilog  ../ethmac/rtl/verilog/eth_rxaddrcheck.v
+#read_verilog  ../ethmac/rtl/verilog/eth_rxcounters.v
+#read_verilog  ../ethmac/rtl/verilog/eth_rxethmac.v
+#read_verilog  ../ethmac/rtl/verilog/eth_rxstatem.v
+#read_verilog  ../ethmac/rtl/verilog/eth_shiftreg.v
+#read_verilog  ../ethmac/rtl/verilog/eth_spram_256x32.v
+#read_verilog  ../ethmac/rtl/verilog/eth_top.v
+#read_verilog  ../ethmac/rtl/verilog/eth_transmitcontrol.v
+#read_verilog  ../ethmac/rtl/verilog/eth_txcounters.v
+#read_verilog  ../ethmac/rtl/verilog/eth_txethmac.v
+#read_verilog  ../ethmac/rtl/verilog/eth_txstatem.v
+#read_verilog  ../ethmac/rtl/verilog/eth_wishbone.v
+#read_verilog  ../ethmac/rtl/verilog/timescale.v
 
 read_verilog  ./external_core_top.v
 
diff --git a/src/ls2.py b/src/ls2.py
index 2284a04..04a10bf 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -696,7 +696,7 @@ def build_platform(fpga, firmware):
 
     # Get Ethernet RMII resource pins
     ethmac_0_pins = None
-    if platform is not None and \
+    if False and platform is not None and \
        fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']:
         # Mainly on X3 connector, MDIO on X4 due to lack of pins
         ethmac_0_ios = [