From: lkcl Date: Thu, 21 Apr 2022 13:08:44 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2645 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fef598db3f12d7997d532d08c1b1cfea3fcb1fa7;p=libreriscv.git --- diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn index cdcddc61e..42a08c5a5 100644 --- a/openpower/sv/biginteger/analysis.mdwn +++ b/openpower/sv/biginteger/analysis.mdwn @@ -204,7 +204,7 @@ detect*). SVP64 has the means to mark registers as scalar or vector. However the available space in the prefix is extremely limited (9 bits). With effectively 5 operands (3 in, 2 out) some compromises are needed. -However a little though gives a useful workaround: two modes, +A little though gives a useful workaround: two modes, controlled by a single bit in `RM.EXTRA`, determine whether the 5th register is set to RC or whether to RT+VL. This then leaves only 4 registers to qualify as scalar/vector, and this can use four