From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 16 Oct 2022 11:08:56 +0000 (+0100)
Subject: rewrite get_idx_out2 in ISACaller to split out
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fefe81874aea854bb68d696c2cc12c59deaa271e;p=openpower-isa.git

rewrite get_idx_out2 in ISACaller to split out
RS/out2 relationship
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index c1a0979b..f6869880 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -579,42 +579,53 @@ def get_idx_out(dec2, name, ewmode=False):
 
 
 # TODO, really should just be using PowerDecoder2
-def get_idx_out2(dec2, name, ewmode=False):
+def get_out2_map(dec2, name):
     # check first if register is activated for write
     op = dec2.dec.op
     out_sel = yield op.out_sel
     out = yield dec2.e.write_ea.data
-    if ewmode:
-        offs = yield dec2.e.write_ea.offs
-        base = yield dec2.e.write_ea.base
-        out = (out, base, offs)
-    o_isvec = yield dec2.o2_isvec
     out_ok = yield dec2.e.write_ea.ok
-    log("get_idx_out2", name, out_sel, out, out_ok, o_isvec)
     if not out_ok:
-        return None, False
+        return False
 
-    if name == 'RA':
+    if name in ['EA', 'RA']:
         if hasattr(op, "upd"):
             # update mode LD/ST uses read-reg A also as an output
             upd = yield op.upd
             log("get_idx_out2", upd, LDSTMode.update.value,
                 out_sel, OutSel.RA.value,
-                out, o_isvec)
+                out)
             if upd == LDSTMode.update.value:
-                return out, o_isvec
+                return True
     if name == 'RS':
         fft_en = yield dec2.implicit_rs
         if fft_en:
             log("get_idx_out2", out_sel, OutSel.RS.value,
-                out, o_isvec)
-            return out, o_isvec
+                out)
+            return True
     if name == 'FRS':
         fft_en = yield dec2.implicit_rs
         if fft_en:
             log("get_idx_out2", out_sel, OutSel.FRS.value,
-                out, o_isvec)
-            return out, o_isvec
+                out)
+            return True
+    return False
+
+
+# TODO, really should just be using PowerDecoder2
+def get_idx_out2(dec2, name, ewmode=False):
+    # check first if register is activated for write
+    op = dec2.dec.op
+    out_sel = yield op.out_sel
+    out = yield dec2.e.write_ea.data
+    if ewmode:
+        offs = yield dec2.e.write_ea.offs
+        base = yield dec2.e.write_ea.base
+        out = (out, base, offs)
+    o_isvec = yield dec2.o2_isvec
+    if get_out2_map(dec2, name):
+        log("get_idx_out2", name, out_sel, out, out_ok, o_isvec)
+        return out, o_isvec
     return None, False