From: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date: Thu, 21 Jun 2018 09:01:21 +0000 (+0000)
Subject: [AArch64][PATCH 1/2] Make AES unspecs commutative
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ff02988392adfa1514e9c3495731b719f5228d5b;p=gcc.git

[AArch64][PATCH 1/2] Make AES unspecs commutative

gcc
2018-06-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi):
	Make opernads of the unspec commutative.

gcc/testsuite
2018-06-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* gcc/gcc.target/aarch64/aes_2.c: New test.

From-SVN: r261835
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d9fbc0c1c55..1731f5a05d2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-06-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi):
+	Make opernads of the unspec commutative.
+
 2018-06-21  Richard Biener  <rguenther@suse.de>
 
 	* tree-data-ref.c (dr_step_indicator): Handle NULL DR_STEP.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index aac5fa146ed..7e9ae086b10 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -5878,7 +5878,7 @@
 
 (define_insn "aarch64_crypto_aes<aes_op>v16qi"
   [(set (match_operand:V16QI 0 "register_operand" "=w")
-        (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
+	(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "%0")
 		       (match_operand:V16QI 2 "register_operand" "w")]
          CRYPTO_AES))]
   "TARGET_SIMD && TARGET_AES"
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2e333b41109..e58afe59ab3 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2018-06-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	* gcc/gcc.target/aarch64/aes_2.c: New test.
+
 2018-06-20  Than McIntosh  <thanm@google.com>
 
 	PR libgcc/86213
diff --git a/gcc/testsuite/gcc.target/aarch64/aes_2.c b/gcc/testsuite/gcc.target/aarch64/aes_2.c
new file mode 100644
index 00000000000..70f113fb5ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/aes_2.c
@@ -0,0 +1,79 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=armv8-a+crypto" } */
+
+#include "arm_neon.h"
+
+uint8x16_t
+test0 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t result;
+  result = vaeseq_u8 (a, b);
+  result = vaeseq_u8 (result, a);
+  return result;
+}
+
+uint8x16_t
+test1 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t result;
+  result = vaeseq_u8 (a, b);
+  result = vaeseq_u8 (a, result);
+  return result;
+}
+
+uint8x16_t
+test2 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t result;
+  result = vaeseq_u8 (b, a);
+  result = vaeseq_u8 (result, b);
+  return result;
+}
+
+uint8x16_t
+test3 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t result;
+  result = vaeseq_u8 (b, a);
+  result = vaeseq_u8 (b, result);
+  return result;
+}
+
+uint8x16_t
+test4 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t result;
+  result = vaesdq_u8 (a, b);
+  result = vaesdq_u8 (result, a);
+  return result;
+}
+
+uint8x16_t
+test5 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t result;
+  result = vaesdq_u8 (a, b);
+  result = vaesdq_u8 (a, result);
+  return result;
+}
+
+uint8x16_t
+test6 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t result;
+  result = vaesdq_u8 (b, a);
+  result = vaesdq_u8 (result, b);
+  return result;
+}
+
+uint8x16_t
+test7 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t result;
+  result = vaesdq_u8 (b, a);
+  result = vaesdq_u8 (b, result);
+  return result;
+}
+/* { dg-final { scan-assembler-not "mov" } } */
+