From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 14 Sep 2014 08:02:00 +0000 (+0200)
Subject: alumacc skeleton
X-Git-Tag: yosys-0.4~138
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ff157fb74fc1b46408c075a0827adbca1b8c496e;p=yosys.git

alumacc skeleton
---

diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index da527ccfe..72998f87b 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -9,6 +9,7 @@ OBJS += passes/techmap/iopadmap.o
 OBJS += passes/techmap/hilomap.o
 OBJS += passes/techmap/extract.o
 OBJS += passes/techmap/maccmap.o
+OBJS += passes/techmap/alumacc.o
 endif
 
 GENFILES += passes/techmap/techmap.inc
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
new file mode 100644
index 000000000..0e2fe4e7f
--- /dev/null
+++ b/passes/techmap/alumacc.cc
@@ -0,0 +1,63 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *  
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/macc.h"
+
+struct AlumaccWorker
+{
+	RTLIL::Module *module;
+
+	AlumaccWorker(RTLIL::Module *module) : module(module)
+	{
+	}
+};
+
+struct AlumaccPass : public Pass {
+	AlumaccPass() : Pass("alumacc", "extract ALU and MACC cells") { }
+	virtual void help()
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    alumacc [selection]\n");
+		log("\n");
+		log("This pass translates arithmetic operations $add, $mul, $lt, etc. to $alu and\n");
+		log("$macc cells.\n");
+		log("\n");
+	}
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		log_header("Executing ALUMACC pass (create $alu and $macc cells).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			// if (args[argidx] == "-foobar") {
+			// 	foobar_mode = true;
+			// 	continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto mod : design->selected_modules()) {
+			AlumaccWorker worker(mod);
+		}
+	}
+} AlumaccPass;
+