From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 27 Nov 2019 21:22:26 +0000 (-0800)
Subject: Add multiple driver testcase
X-Git-Tag: working-ls180~778^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ff1e35768224a7824ec9838ca84d27bbb4a14676;p=yosys.git

Add multiple driver testcase
---

diff --git a/tests/various/submod.ys b/tests/various/submod.ys
index 552fd4e01..9d7dabdd7 100644
--- a/tests/various/submod.ys
+++ b/tests/various/submod.ys
@@ -15,6 +15,7 @@ proc
 design -save gold
 
 submod
+check -assert
 design -stash gate
 
 design -import gold -as gold
@@ -41,6 +42,7 @@ proc
 design -save gold
 
 submod
+check -assert top
 design -stash gate
 
 design -import gold -as gold
@@ -50,6 +52,35 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 
+design -reset
+read_verilog <<EOT
+module top(input a, output [1:0] b, c);
+(* submod="bar" *) sub s1(a, b[0]);
+(* submod="bar" *) sub s2(a, c[1]);
+assign c = b;
+endmodule
+
+module sub(input a, output c);
+assign c = a;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+design -save gold
+
+submod
+check -assert top
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+
+
 design -reset
 read_verilog -icells <<EOT
 module top(input d, c, (* init = 3'b011 *) output reg [2:0] q);