From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 10 Apr 2015 15:18:07 +0000 (+0200)
Subject: fhdl/verilog: avoid reg initialization in printheader when reset is not an int.
X-Git-Tag: 24jan2021_ls180~2099^2~116
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ff23960657faccf656f0f4f9d749194dc180e6c4;p=litex.git

fhdl/verilog: avoid reg initialization in printheader when reset is not an int.

We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index c1cfc690..eac214c6 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -172,7 +172,11 @@ def _printheader(f, ios, name, ns):
 		if sig in wires:
 			r += "wire " + _printsig(ns, sig) + ";\n"
 		else:
-			r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
+			if isinstance(sig.reset, int):
+				resetexpr = " = " + _printexpr(ns, sig.reset)[0]
+			else:
+				resetexpr = ""
+			r += "reg " + _printsig(ns, sig) + resetexpr + ";\n"
 	r += "\n"
 	return r