From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Dec 2019 21:38:32 +0000 (-0800)
Subject: Put specify/endspecify inside ``
X-Git-Tag: working-ls180~907
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ff2645ce0b8d0e639b0e83db35476036dde34f0d;p=yosys.git

Put specify/endspecify inside ``
---

diff --git a/README.md b/README.md
index 5cc52e842..0250c7846 100644
--- a/README.md
+++ b/README.md
@@ -454,10 +454,10 @@ Verilog Attributes and non-standard features
   expressions over parameters and constant values are allowed). The intended
   use for this is synthesis-time DRC.
 
-- There is limited support for converting specify .. endspecify statements to
-  special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in
-  blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this
-  functionality. (By default specify .. endspecify blocks are ignored.)
+- There is limited support for converting ``specify`` .. ``endspecify``
+  statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells,
+  for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to
+  enable this functionality. (By default these blocks are ignored.)
 
 
 Non-standard or SystemVerilog features for formal verification