From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 2 Dec 2021 14:55:54 +0000 (+0000)
Subject: add module to regspec_decode_* and get_rdflags
X-Git-Tag: sv_maxu_works-initial~675
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ff270dfa98fcdf4b400e97add412c4415340e072;p=openpower-isa.git

add module to regspec_decode_* and get_rdflags
---

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 49ab5066..9a2a7394 100644
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -1599,11 +1599,14 @@ class PowerDecode2(PowerDecodeSubset):
         comb += self.do_copy("svstate", self.state.svstate, True)  # SVSTATE
 
 
-def get_rdflags(e, cu):
+def get_rdflags(m, e, cu):
+    """returns a sequential list of the read "ok" flags for a given FU.
+    this list is in order of the CompUnit input specs
+    """
     rdl = []
     for idx in range(cu.n_src):
         regfile, regname, _ = cu.get_in_spec(idx)
-        rdflag, read = regspec_decode_read(e, regfile, regname)
+        rdflag, read = regspec_decode_read(m, e, regfile, regname)
         rdl.append(rdflag)
     log("rdflags", rdl)
     return Cat(*rdl)
diff --git a/src/openpower/decoder/power_regspec_map.py b/src/openpower/decoder/power_regspec_map.py
index 4a738557..ecea6c9c 100644
--- a/src/openpower/decoder/power_regspec_map.py
+++ b/src/openpower/decoder/power_regspec_map.py
@@ -40,7 +40,7 @@ from openpower.decoder.power_enums import CryIn
 from openpower.util import log
 
 
-def regspec_decode_read(e, regfile, name):
+def regspec_decode_read(m, e, regfile, name):
     """regspec_decode_read
     """
 
@@ -122,7 +122,7 @@ def regspec_decode_read(e, regfile, name):
     assert False, "regspec not found %s %s" % (regfile, name)
 
 
-def regspec_decode_write(e, regfile, name):
+def regspec_decode_write(m, e, regfile, name):
     """regspec_decode_write
     """
 
@@ -199,8 +199,8 @@ def regspec_decode_write(e, regfile, name):
     assert False, "regspec not found %s %s" % (regfile, name)
 
 
-def regspec_decode(readmode, e, regfile, name):
+def regspec_decode(m, readmode, e, regfile, name):
     if readmode:
-        return regspec_decode_read(e, regfile, name)
-    return regspec_decode_write(e, regfile, name)
+        return regspec_decode_read(m, e, regfile, name)
+    return regspec_decode_write(m, e, regfile, name)