From: Jordan Justen <jordan.l.justen@intel.com>
Date: Sat, 2 Apr 2016 08:25:05 +0000 (-0700)
Subject: genxml/hsw: Add L3 cache control registers
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ff417388719828b3b5f0c9e3c0b076e9cff99ff7;p=mesa.git

genxml/hsw: Add L3 cache control registers

These were added to the i965 driver in
5912da45a69923afa1b7f2eb5bb371d848813c41.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
---

diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 698d93f12ae..2258dee3960 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2932,4 +2932,12 @@
     <field name="T Low Bandwidth" start="21" end="21" type="uint"/>
   </register>
 
+  <register name="SCRATCH1" length="1" num="0xb038">
+    <field name="L3 Atomic Disable" start="27" end="27" type="uint"/>
+  </register>
+
+  <register name="CHICKEN3" length="1" num="0xe49c">
+    <field name="L3 Atomic Disable" start="6" end="6" type="uint"/>
+  </register>
+
 </genxml>