From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 May 2020 12:51:50 +0000 (+0100)
Subject: whitespace
X-Git-Tag: convert-csv-opcode-to-binary~2663
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ff48d3acdc0cef8e62205cfa00934fd9c5fa59e3;p=libreriscv.git

whitespace
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diff --git a/resources.mdwn b/resources.mdwn
index 7ed10e4c1..f78561c57 100644
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -265,7 +265,12 @@ ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizze
   and parameterizeable CSRs.
 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
 
-* There is a great guy, Robert Baruch, who has a good [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen. He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put [the code](https://github.com/RobertBaruch/n6800) and [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw) online.
+* There is a great guy, Robert Baruch, who has a good
+  [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
+  He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put
+  [the code](https://github.com/RobertBaruch/n6800) and
+  [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
+  online.
 
 * [Minerva](https://github.com/lambdaconcept/minerva)
   An SOC written in Python nMigen DSL