From: Florent Kermarrec Date: Tue, 7 May 2019 16:44:03 +0000 (+0200) Subject: boards/targets: make sys_clk_freq a parameter X-Git-Tag: 24jan2021_ls180~1234 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ff5179153c9142f49806121213589f1cfd63bb5a;p=litex.git boards/targets: make sys_clk_freq a parameter Most of the targets can now generate an abritrary sys_clk_freq from onboard XO. --- diff --git a/litex/boards/targets/ac701.py b/litex/boards/targets/ac701.py index a0b4ba5a..0933866e 100755 --- a/litex/boards/targets/ac701.py +++ b/litex/boards/targets/ac701.py @@ -51,9 +51,8 @@ class BaseSoC(SoCSDRAM): "ddrphy": 16, } csr_map.update(SoCSDRAM.csr_map) - def __init__(self, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = ac701.Platform() - sys_clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index ba058c5f..98cc0adc 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -55,9 +55,8 @@ class BaseSoC(SoCSDRAM): "ddrphy": 16, } csr_map.update(SoCSDRAM.csr_map) - def __init__(self, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = arty.Platform() - sys_clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index c51c1a11..81a3e4a2 100755 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -96,9 +96,9 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): + assert sys_clk_freq == int(100e6) platform = de0nano.Platform() - sys_clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, **kwargs) diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index efd73979..1b9e1d6c 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -46,9 +46,8 @@ class BaseSoC(SoCSDRAM): "ddrphy": 16, } csr_map.update(SoCSDRAM.csr_map) - def __init__(self, **kwargs): + def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = genesys2.Platform() - sys_clk_freq = int(125e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 14b53239..954fe954 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -46,9 +46,8 @@ class BaseSoC(SoCSDRAM): "ddrphy": 16, } csr_map.update(SoCSDRAM.csr_map) - def __init__(self, **kwargs): + def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = kc705.Platform() - sys_clk_freq = int(125e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index 06eda9e2..9067ceed 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -82,9 +82,8 @@ class BaseSoC(SoCSDRAM): "ddrphy": 16, } csr_map.update(SoCSDRAM.csr_map) - def __init__(self, **kwargs): + def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = kcu105.Platform() - sys_clk_freq = int(125e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py index 20e2113e..dbd39251 100755 --- a/litex/boards/targets/minispartan6.py +++ b/litex/boards/targets/minispartan6.py @@ -81,9 +81,9 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, **kwargs): + def __init__(self, sys_clk_freq=int(80e6), **kwargs): + assert sys_clk_freq == int(80e6) platform = minispartan6.Platform() - sys_clk_freq = int(80e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, **kwargs) diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index 5adf51d8..56df5182 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -47,9 +47,8 @@ class BaseSoC(SoCSDRAM): "ddrphy": 16, } csr_map.update(SoCSDRAM.csr_map) - def __init__(self, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = nexys4ddr.Platform() - sys_clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index d949f57a..7125d1a6 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -50,9 +50,8 @@ class BaseSoC(SoCSDRAM): "ddrphy": 16, } csr_map.update(SoCSDRAM.csr_map) - def __init__(self, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = nexys_video.Platform() - sys_clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 9e807d62..2c88a661 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -17,7 +17,7 @@ from litedram.phy import GENSDRPHY # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): - def __init__(self, platform): + def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) @@ -35,8 +35,8 @@ class _CRG(Module): self.submodules.pll = pll = ECP5PLL() self.comb += pll.reset.eq(rst) pll.register_clkin(clk25, 25e6) - pll.create_clkout(self.cd_sys, 50e6, phase=11) - pll.create_clkout(self.cd_sys_ps, 50e6, phase=20) + pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11) + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20) self.specials += AsyncResetSynchronizer(self.cd_sys, rst) # sdram clock @@ -56,7 +56,7 @@ class BaseSoC(SoCSDRAM): integrated_rom_size=0x8000, **kwargs) - self.submodules.crg = _CRG(platform) + self.submodules.crg = _CRG(platform, sys_clk_freq) if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index e28ccb3e..bb92c132 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -77,9 +77,8 @@ class BaseSoC(SoCSDRAM): "ddrphy": 16, } csr_map.update(SoCSDRAM.csr_map) - def __init__(self, toolchain="diamond", **kwargs): + def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs): platform = versa_ecp5.Platform(toolchain=toolchain) - sys_clk_freq = int(75e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, **kwargs)