From: lkcl <lkcl@web>
Date: Thu, 5 May 2022 15:05:10 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2445
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ff526a3654bc070e08580726afc4ccfae6e5d13d;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index a1d0701d3..13673403d 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -87,9 +87,17 @@ Ecosystem?
   making its way into data centres.
 * OpenRISC, an entirely Open ISA suitable for embedded systems.
 * s390, a Mainframe ISA very similar to Power.
-* Power ISA, a Supercomputing-class ISA.
+* Power ISA, a Supercomputing-class ISA, as demonstrated by
+  two out of three of the top500.org supercomputers using
+  160,000 IBM POWER9 Cores.
 * ARC, a competitor at the time to ARM, best known for use in
   Broadcom VideoCore IV.
+* RISC-V, with a software ecosystem heavily in development
+  and with rapid adoption 
+  in an uncontrolled fashion, is set on an unstoppable
+  and inevitable trainwreck path to replicate the
+  opcode conflict nightmare that plagued the Power ISA,
+  two decades ago.
 * Tensilica, Andes STAR and Western Digital for successful
   commercial proprietary ISAs: Tensilica in Baseband Modems,
   Andes in Audio DSPs, WD in HDDs and SSDs. These are all