From: lkcl <lkcl@web>
Date: Sat, 9 Apr 2022 20:22:08 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2821
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ff5dc81dd4963755497e149fdd13b853b72722ad;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index b402f41a0..4de564e3f 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -147,6 +147,13 @@ could have been decided
 that RA would be indexed 0 (EXTRA bits 0-2), RB indexed 1 (EXTRA bits 3-5)
 and RT indexed 2 (EXTRA bits 6-8).
 
+Fourthly, the instruction was analysed to see if Twin or Single
+Predication was suitable.  As a general rule this was if there
+was only a single operand and a single result (`extw` and LD/ST)
+however some 2 or 3 operand instructions also qualify.
+
+Fifthly, 
+
 # Single Predication
 
 This is a standard mode normally found in Vector ISAs.  every element in every source Vector and in the destination uses the same bit of one single predicate mask.