From: Tim 'mithro' Ansell <mithro@mithis.com>
Date: Sun, 29 Oct 2017 17:39:01 +0000 (-0700)
Subject: Bump the IRQ for liteeth based targets.
X-Git-Tag: 24jan2021_ls180~1799^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ff72757b870d6ac810cba7fcf8c5400a163e8340;p=litex.git

Bump the IRQ for liteeth based targets.
---

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 75d58a9b..64d892f8 100755
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -124,7 +124,7 @@ class MiniSoC(BaseSoC):
     csr_map.update(BaseSoC.csr_map)
 
     interrupt_map = {
-        "ethmac": 2,
+        "ethmac": 3,
     }
     interrupt_map.update(BaseSoC.interrupt_map)
 
diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 37297f33..541d3dea 100755
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -104,7 +104,7 @@ class MiniSoC(BaseSoC):
     csr_map.update(BaseSoC.csr_map)
 
     interrupt_map = {
-        "ethmac": 2,
+        "ethmac": 3,
     }
     interrupt_map.update(BaseSoC.interrupt_map)
 
diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 75774e94..77b54688 100755
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -113,7 +113,7 @@ class MiniSoC(BaseSoC):
     csr_map.update(BaseSoC.csr_map)
 
     interrupt_map = {
-        "ethmac": 2,
+        "ethmac": 3,
     }
     interrupt_map.update(BaseSoC.interrupt_map)
 
diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index 1624441f..04371fd9 100755
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -68,7 +68,7 @@ class MiniSoC(BaseSoC):
     csr_map.update(BaseSoC.csr_map)
 
     interrupt_map = {
-        "ethmac": 2,
+        "ethmac": 3,
     }
     interrupt_map.update(BaseSoC.interrupt_map)
 
diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py
index 179581b4..88c8afd3 100755
--- a/litex/boards/targets/simple.py
+++ b/litex/boards/targets/simple.py
@@ -30,7 +30,7 @@ class MiniSoC(BaseSoC):
     csr_map.update(BaseSoC.csr_map)
 
     interrupt_map = {
-        "ethmac": 2,
+        "ethmac": 3,
     }
     interrupt_map.update(BaseSoC.interrupt_map)