From: Jan Beulich Date: Mon, 22 Jul 2019 08:07:29 +0000 (+0000) Subject: x86/AVX512: improve generated code for bit-wise negation of vectors of integers X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ff8f129bc2f57fdfc80f56d73b84a80948d11d84;p=gcc.git x86/AVX512: improve generated code for bit-wise negation of vectors of integers NOT on vectors of integers does not require loading a constant vector of all ones into a register - VPTERNLOG can be used here (and could/should be further used to carry out other binary and ternary logical operations which don't have a special purpose instruction). gcc/ 2019-07-22 Jan Beulich * config/i386/sse.md (ternlogsuffix): New. (one_cmpl2): Don't force CONSTM1_RTX into a register when AVX512F is in use. (one_cmpl2): New. From-SVN: r273663 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 05d8efaf971..3e861effcd5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-07-22 Jan Beulich + + * config/i386/sse.md (ternlogsuffix): New. + (one_cmpl2): Don't force CONSTM1_RTX into a register when + AVX512F is in use. + (one_cmpl2): New. + 2019-07-22 Martin Liska * config/avr/avr.c (avr_asm_output_aligned_decl_common): Update diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 12d6dc0cb7e..8abd1617b6f 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -853,6 +853,13 @@ (V4SF "k") (V2DF "q") (SF "k") (DF "q")]) +;; Mapping of vector modes to VPTERNLOG suffix +(define_mode_attr ternlogsuffix + [(V8DI "q") (V4DI "q") (V2DI "q") + (V16SI "d") (V8SI "d") (V4SI "d") + (V32HI "d") (V16HI "d") (V8HI "d") + (V64QI "d") (V32QI "d") (V16QI "d")]) + ;; Number of scalar elements in each vector type (define_mode_attr ssescalarnum [(V64QI "64") (V16SI "16") (V8DI "8") @@ -12723,9 +12730,22 @@ (match_dup 2)))] "TARGET_SSE" { - operands[2] = force_reg (mode, CONSTM1_RTX (mode)); + if (!TARGET_AVX512F) + operands[2] = force_reg (mode, CONSTM1_RTX (mode)); + else + operands[2] = CONSTM1_RTX (mode); }) +(define_insn "one_cmpl2" + [(set (match_operand:VI 0 "register_operand" "=v") + (xor:VI (match_operand:VI 1 "nonimmediate_operand" "vm") + (match_operand:VI 2 "vector_all_ones_operand" "BC")))] + "TARGET_AVX512F" + "vpternlog\t{$0x55, %1, %0, %0|%0, %0, %1, 0x55}" + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_expand "_andnot3" [(set (match_operand:VI_AVX2 0 "register_operand") (and:VI_AVX2