From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 4 Dec 2023 09:45:23 +0000 (-0800)
Subject: test/ldst: add fixedsync tests for b/h/w/d ll/sc, but not quadword
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ffaaa6a3e0a24cbd263ccc35e4fe47710b531326;p=openpower-isa.git

test/ldst: add fixedsync tests for b/h/w/d ll/sc, but not quadword

quadword probably doesn't work correctly and probably requires a bit of work
---

diff --git a/src/openpower/decoder/isa/test_caller_fixedsync.py b/src/openpower/decoder/isa/test_caller_fixedsync.py
new file mode 100644
index 00000000..e005bdcb
--- /dev/null
+++ b/src/openpower/decoder/isa/test_caller_fixedsync.py
@@ -0,0 +1,23 @@
+""" sync tests
+"""
+
+import unittest
+
+from openpower.test.ldst.fixedsync_cases import FixedSyncCases
+from openpower.test.runner import TestRunnerBase
+
+# writing the test_caller invocation this way makes it work with pytest
+
+
+class TestFixedSync(TestRunnerBase):
+    def __init__(self, test):
+        assert test == 'test'
+        super().__init__(FixedSyncCases().test_data)
+
+    def test(self):
+        # dummy function to make unittest try to test this class
+        pass
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/src/openpower/test/ldst/fixedsync_cases.py b/src/openpower/test/ldst/fixedsync_cases.py
new file mode 100644
index 00000000..d5a7e300
--- /dev/null
+++ b/src/openpower/test/ldst/fixedsync_cases.py
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: LGPLv3+
+# Copyright (C) 2023 Jacob Lifshay <programmerjake@gmail.com>
+# Funded by NLnet http://nlnet.nl
+""" fixedsync test cases
+
+related bugs:
+
+* https://bugs.libre-soc.org/show_bug.cgi?id=1228
+"""
+
+from openpower.test.common import TestAccumulatorBase, skip_case
+from openpower.test.state import ExpectedState
+from openpower.test.util import assemble
+
+
+class FixedSyncCases(TestAccumulatorBase):
+    def case_lxarx_stxcx(self):
+        # TODO: test quadword instructions too
+        for mnemonic, bit_width in ('b', 8), ('h', 16), ('w', 32), ('d', 64):
+            with self.subTest(mnemonic=mnemonic, bit_width=bit_width):
+                prog = assemble(["l%sarx 3, 4, 5, 0" % (mnemonic,),
+                                "st%scx. 6, 4, 5" % (mnemonic,)])
+                gprs = [0] * 32
+                gprs[4] = 0x12000
+                gprs[5] = 0x340
+                gprs[6] = 0xD5C987D5CCD52AF2
+                mem_value = 0x6E18_B505_27EA_93B9
+                initial_mem = {0x12340: (0x6E18_B505_27EA_93B9, 8)}
+                e = ExpectedState(pc=8, int_regs=gprs)
+                e.intregs[3] = mem_value % (2 ** bit_width)
+                e.crregs[0] = 0x2
+                mem_value -= mem_value % (2 ** bit_width)
+                mem_value += gprs[6] % (2 ** bit_width)
+                e.mem = {
+                    0x12340: mem_value,
+                }
+                self.add_case(prog, initial_regs=gprs,
+                              initial_mem=initial_mem, expected=e)
+
+    def case_lxarx_stxcx_different(self):
+        # TODO: test quadword instructions too
+        for mnemonic, bit_width in ('b', 8), ('h', 16), ('w', 32), ('d', 64):
+            with self.subTest(mnemonic=mnemonic, bit_width=bit_width):
+                prog = assemble(["l%sarx 3, 4, 5, 0" % (mnemonic,),
+                                "st%scx. 6, 0, 5" % (mnemonic,)])
+                gprs = [0] * 32
+                gprs[4] = 0x12000
+                gprs[5] = 0x340
+                gprs[6] = 0xD5C987D5CCD52AF2
+                mem_value = 0x6E18_B505_27EA_93B9
+                initial_mem = {0x12340: (0x6E18_B505_27EA_93B9, 8)}
+                e = ExpectedState(pc=8, int_regs=gprs)
+                e.intregs[3] = mem_value % (2 ** bit_width)
+                e.crregs[0] = 0x0
+                e.mem = {
+                    0x12340: mem_value,
+                }
+                self.add_case(prog, initial_regs=gprs,
+                              initial_mem=initial_mem, expected=e)
+
+    def case_lxarx_stxcx_stxcx(self):
+        # TODO: test quadword instructions too
+        for mnemonic, bit_width in ('b', 8), ('h', 16), ('w', 32), ('d', 64):
+            with self.subTest(mnemonic=mnemonic, bit_width=bit_width):
+                prog = assemble(["l%sarx 3, 4, 5, 0" % (mnemonic,),
+                                 "st%scx. 6, 0, 5" % (mnemonic,),
+                                 "st%scx. 6, 4, 5" % (mnemonic,)])
+                gprs = [0] * 32
+                gprs[4] = 0x12000
+                gprs[5] = 0x340
+                gprs[6] = 0xD5C987D5CCD52AF2
+                mem_value = 0x6E18_B505_27EA_93B9
+                initial_mem = {0x12340: (0x6E18_B505_27EA_93B9, 8)}
+                e = ExpectedState(pc=12, int_regs=gprs)
+                e.intregs[3] = mem_value % (2 ** bit_width)
+                e.crregs[0] = 0x0
+                e.mem = {
+                    0x12340: mem_value,
+                }
+                self.add_case(prog, initial_regs=gprs,
+                              initial_mem=initial_mem, expected=e)