From: lkcl <lkcl@web>
Date: Fri, 10 Sep 2021 12:51:34 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~168
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ffae6a9b2e9df1c2287144261d372d8e8887db2a;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 7eb890f09..f3983a220 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -3,6 +3,7 @@
 Links:
 
 * <https://bugs.libre-soc.org/show_bug.cgi?id=687>
+* [[svp64]]
 
 Condition Register Fields are only 4 bits wide: this presents some
 interesting conceptual challenges for SVP64, particularly with respect to element