From: Olof Kindgren Date: Thu, 25 Jun 2015 23:15:34 +0000 (+0200) Subject: litesata/example_designs: Add missing clock in phy instantiation X-Git-Tag: 24jan2021_ls180~2221^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ffb6081720eb1d4254dd774680d5b203e65cd271;p=litex.git litesata/example_designs: Add missing clock in phy instantiation --- diff --git a/misoclib/mem/litesata/example_designs/targets/core.py b/misoclib/mem/litesata/example_designs/targets/core.py index d841d4ec..e15b259a 100644 --- a/misoclib/mem/litesata/example_designs/targets/core.py +++ b/misoclib/mem/litesata/example_designs/targets/core.py @@ -17,7 +17,7 @@ class Core(Module): self.clk_freq = clk_freq # SATA PHY/Core/Frontend - self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq) + self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sys_clk"), platform.request("sata"), "sata_gen2", clk_freq) self.submodules.sata_core = LiteSATACore(self.sata_phy) self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)