From: Cesar Strauss <cestrauss@gmail.com>
Date: Mon, 6 Jul 2020 08:53:57 +0000 (-0300)
Subject: Simplify waiting loops
X-Git-Tag: div_pipeline~162^2~42
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ffc1e56a19515ae871cb8114df18f110c7ef1437;p=soc.git

Simplify waiting loops
---

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 4afc491e..ae4fb2c0 100644
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -484,11 +484,9 @@ def test_alu_parallel():
         yield dut.op.insn_type.eq(op)
         yield dut.op.invert_a.eq(inv_a)
         yield dut.p.valid_i.eq(1)
-        while True:
+        yield
+        while not (yield dut.p.ready_o):
             yield
-            rdy = yield dut.p.ready_o
-            if rdy:
-                break
         yield dut.p.valid_i.eq(0)
         yield dut.a.eq(0)
         yield dut.b.eq(0)
@@ -498,10 +496,7 @@ def test_alu_parallel():
     def receive():
         yield dut.n.ready_i.eq(1)
         yield
-        while True:
-            valid = yield dut.n.valid_o
-            if valid:
-                break
+        while not (yield dut.n.valid_o):
             yield
         result = yield dut.o
         yield dut.n.ready_i.eq(0)