From: lkcl <lkcl@web>
Date: Sun, 1 Aug 2021 22:16:55 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~546
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ffd518d0873455612b05c105509b9e448a2c6de4;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 982545e64..34528649c 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -198,7 +198,8 @@ These are the modes:
 
 Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations.  ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result.  normal, saturate and pred-result are however inter-element independent and may easily be parallelised to give high performance, regardless of the value of VL.
 
-The Mode table for operations except LD/ST is laid out as follows:
+The Mode table for operations except LD/ST and Branch Conditional
+ is laid out as follows:
 
 | 0-1 |  2  |  3   4  |  description              |
 | --- | --- |---------|-------------------------- |