From: Tobias Platen <tplaten@posteo.de>
Date: Sat, 30 Apr 2022 17:42:42 +0000 (+0200)
Subject: change frequency for orangecrab, correct uart output
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ffdb2f24a3146c548a1f01329d2390649c4d209f;p=ls2.git

change frequency for orangecrab, correct uart output
---

diff --git a/src/ls2.py b/src/ls2.py
index 89d6c06..d236ff2 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -872,7 +872,7 @@ def build_platform(fpga, firmware):
     if fpga == 'ulx3s':
         clk_freq = 40.0e6
     if fpga == 'orangecrab':
-        clk_freq = 50e6
+        clk_freq = 40.0e6
 
     # merge dram_clk_freq with clk_freq if the same
     if clk_freq == dram_clk_freq:
@@ -896,7 +896,7 @@ def build_platform(fpga, firmware):
     if platform is not None:
         if fpga=="orangecrab":
             # assumes an FT232 USB-UART soldered onto these two pins.
-            orangecrab_uart = UARTResource(0, rx="N17", tx="M18")
+            orangecrab_uart = UARTResource(0, rx="M18", tx="N17")
             platform.add_resources([orangecrab_uart])
 
         uart_pins = platform.request("uart", 0)