From: Raptor Engineering Development Team <support@raptorengineering.com>
Date: Thu, 7 Apr 2022 20:23:22 +0000 (-0500)
Subject: Re-apply part of 180026c72f0e1d3ef365b2214288d4a543a238dd
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ffdcef6b591e73932a97278e011834c8303731cc;p=gram.git

Re-apply part of 180026c72f0e1d3ef365b2214288d4a543a238dd

The rank decoder inversion was incorrectly removed in
commit 03e79da11c95b3fa3a2e55a4c08af8521c4d2283

Tested to give valid memtest output over UART bridge
---

diff --git a/gram/core/multiplexer.py b/gram/core/multiplexer.py
index fe5fc6f..87ea8a9 100644
--- a/gram/core/multiplexer.py
+++ b/gram/core/multiplexer.py
@@ -173,9 +173,9 @@ class _Steerer(Elaboratable):
                     with m.If(sel == STEER_REFRESH):
                         m.d.sync += phase.cs_n.eq(0)
                     with m.Else():
-                        m.d.sync += phase.cs_n.eq(rank_decoder.o)
+                        m.d.sync += phase.cs_n.eq(~rank_decoder.o)
                 else:
-                    m.d.sync += phase.cs_n.eq(rank_decoder.o)
+                    m.d.sync += phase.cs_n.eq(~rank_decoder.o)
                 m.d.sync += phase.bank.eq(Array(cmd.ba[:-rankbits] for cmd in self.commands)[sel])
             else:
                 m.d.sync += [