From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 9 Oct 2021 19:52:14 +0000 (+0100)
Subject: altered test_partsig2.py removed outval, run with outval2 instead
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fff08681b2e012b6f2b2ee8506216d753b74fa0e;p=ieee754fpu.git

altered test_partsig2.py removed outval, run with outval2 instead
---

diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py
index 1830af12..f5294a84 100644
--- a/src/ieee754/part/test/test_partsig.py
+++ b/src/ieee754/part/test/test_partsig.py
@@ -322,9 +322,8 @@ class TestMux(unittest.TestCase):
                         outval2 = (yield module.mux_out2)
                         msg = f"{msg_prefix}: mux " + \
                             f"0x{sel:X} ? 0x{a:X} : 0x{b:X}" + \
-                            f" => 0x{y:X} != 0x{outval:X}, masklist %s"
+                            f" => 0x{y:X} != 0x{outval2:X}, masklist %s"
                         # print ((msg % str(maskbit_list)).format(locals()))
-                        self.assertEqual(y, outval, msg % str(maskbit_list))
                         self.assertEqual(y, outval2, msg % str(maskbit_list))
 
             yield part_mask.eq(0)