From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Wed, 31 May 2023 21:05:08 +0000 (+0300)
Subject: power_insn: disassemble RA0 and RT0 correctly
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=refs%2Fheads%2Fextras;p=openpower-isa.git

power_insn: disassemble RA0 and RT0 correctly
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index d480a3f3..ca540386 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1286,6 +1286,9 @@ class ExtendableOperand(DynamicOperand):
             style=Style.NORMAL, prefix="", indent=""):
         (vector, value, span) = self.sv_spec(insn=insn)
 
+        if (self.extra_reg.or_zero and (value == 0)):
+            prefix = ""
+
         if style >= Style.VERBOSE:
             mode = "vector" if vector else "scalar"
             yield f"{indent}{self.name} ({mode})"