From: Stefan Riesenberger <stefan.riesenberger@gmail.com>
Date: Fri, 9 Apr 2021 13:44:08 +0000 (+0200)
Subject: sf2: fix name of AND modules
X-Git-Tag: yosys-0.10~219
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=refs%2Fheads%2Fls180;p=yosys.git

sf2: fix name of AND modules
---

diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v
index eff57a655..4b57bad7b 100644
--- a/techlibs/sf2/cells_sim.v
+++ b/techlibs/sf2/cells_sim.v
@@ -1,20 +1,20 @@
 // https://coredocs.s3.amazonaws.com/Libero/12_0_0/Tool/sf2_mlg.pdf
 
-module ADD2 (
+module AND2 (
 	input A, B,
 	output Y
 );
 	assign Y = A & B;
 endmodule
 
-module ADD3 (
+module AND3 (
 	input A, B, C,
 	output Y
 );
 	assign Y = A & B & C;
 endmodule
 
-module ADD4 (
+module AND4 (
 	input A, B, C, D,
 	output Y
 );