From: Sadoon Albader Date: Tue, 9 Jan 2024 16:34:53 +0000 (+0300) Subject: added dsrd implementation of first half of blocks X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=refs%2Fheads%2Fpoly1305_svp64;p=openpower-isa.git added dsrd implementation of first half of blocks --- diff --git a/crypto/poly1305/poly1305-donna-test.py b/crypto/poly1305/poly1305-donna-test.py index 999d9a04..2637b188 100644 --- a/crypto/poly1305/poly1305-donna-test.py +++ b/crypto/poly1305/poly1305-donna-test.py @@ -238,6 +238,31 @@ class Poly1305Donna(object): lst = list(lst) final_regs = simulation_svp(lst, initial_regs) + initial_regs = [0] * 32 + initial_regs[0] = t0 + initial_regs[1] = t1 + initial_regs[2] = 20 + initial_regs[3] = 24 + initial_regs[4] = 44 + initial_regs[5] = hibit + initial_regs[20] = h2 + initial_regs[21] = h1 + initial_regs[22] = h0 + + # Syntax : dsrd RT,RA,RB,RC + # or RT,RC = DSRD(RA,RB) + lst = SVP64Asm([ + 'dsrd 11, 1, 3, 12', + 'dsrd 6, 0, 4, 13', + 'setvl 0, 0, 2, 0, 1, 1', + 'sv.rldicl *12, *12, %d, 20' %(64-20), + 'sv.or *11, *11, *5', + 'setvl 0, 0, 3, 0, 1, 1', + 'sv.add *20, *20, *11' + ]) + lst = list(lst) + final_regs_dsrd = simulation_svp(lst, initial_regs) + h0 += t0 & 0xfffffffffff; h1 += (((t0 >> 44) | (t1 << 20)) & 0xfffffffffff); h2 += (((t1 >> 24) ) & 0x3ffffffffff) | hibit; @@ -246,6 +271,10 @@ class Poly1305Donna(object): assert (h1 == final_regs[4].value), "h1 and h1_sim are uneqaul!" assert (h2 == final_regs[5].value), "h2 and h2_sim are unequal!" + assert (h0 == final_regs_dsrd[22].value), "h0 and h0_dsrd are unequal!" + assert (h1 == final_regs_dsrd[21].value), "h1 and h1_dsrd are uneqaul!" + assert (h2 == final_regs_dsrd[20].value), "h2 and h2_dsrd are unequal!" + print(" loop h+t %x %x %x" % (h0, h1, h2)) #/* h *= r */