From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Mar 2018 05:10:01 +0000 (+0000)
Subject: add IOF 2 and 3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=refs%2Fheads%2Fshakti_iclass;p=sifive-blocks.git

add IOF 2 and 3
---

diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala
index a1b166f..12dc57f 100644
--- a/src/main/scala/devices/gpio/GPIO.scala
+++ b/src/main/scala/devices/gpio/GPIO.scala
@@ -79,6 +79,8 @@ class GPIOPortIO(private val c: GPIOParams) extends Bundle {
   val pins = Vec(c.width, new EnhancedPin())
   val iof_0 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
   val iof_1 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
+  val iof_2 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
+  val iof_3 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
 }
 
 // It would be better if the IOF were here and
@@ -197,7 +199,17 @@ trait HasGPIOModuleContents extends MultiIOModule with HasRegMap {
         iof1Ctrl(pin)    <> io.port.iof_1.get(pin).o
       }
 
-      // Select IOF 0 vs. IOF 1.
+      iof2Ctrl(pin)      <> swPinCtrl(pin)
+      when (io.port.iof_2.get(pin).o.valid) {
+        iof1Ctrl(pin)    <> io.port.iof_2.get(pin).o
+      }
+
+      iof2Ctrl(pin)      <> swPinCtrl(pin)
+      when (io.port.iof_3.get(pin).o.valid) {
+        iof1Ctrl(pin)    <> io.port.iof_3.get(pin).o
+      }
+
+      // Select IOF 0 vs. IOF 1 vs. IOF 2 vs. IOF 3.
       iofCtrl(pin)       <> Mux(iofSelReg(pin), iof1Ctrl(pin), iof0Ctrl(pin))
 
       // Allow SW Override for things IOF doesn't control.
@@ -223,6 +235,8 @@ trait HasGPIOModuleContents extends MultiIOModule with HasRegMap {
       // Send Value to all consumers
       io.port.iof_0.get(pin).i.ival := inSyncReg(pin)
       io.port.iof_1.get(pin).i.ival := inSyncReg(pin)
+      io.port.iof_2.get(pin).i.ival := inSyncReg(pin)
+      io.port.iof_3.get(pin).i.ival := inSyncReg(pin)
     }
   }
 }