From: Wesley W. Terpstra <wesley@sifive.com>
Date: Thu, 10 Aug 2017 20:26:28 +0000 (-0700)
Subject: uart: output JSON pointing to the TX registers for tapping output
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=refs%2Fheads%2Fuart-json;p=sifive-blocks.git

uart: output JSON pointing to the TX registers for tapping output
---

diff --git a/src/main/scala/devices/uart/UART.scala b/src/main/scala/devices/uart/UART.scala
index 58722e1..3612bce 100644
--- a/src/main/scala/devices/uart/UART.scala
+++ b/src/main/scala/devices/uart/UART.scala
@@ -69,10 +69,12 @@ class UARTTx(c: UARTParams)(implicit p: Parameters) extends UARTModule(c)(p) {
   val out = Reg(init = Bits(1, 1))
   io.out := out
 
+  // Report the UART registers so we can backdoor functionality in simulation
+  ElaborationArtefacts.add(f"uart-${c.address}%x.json", s"""{"counter":["${counter.pathName}"],"shifter":["${shifter.pathName}"]}\n""")
+
   val busy = (counter =/= UInt(0))
   io.in.ready := io.en && !busy
   when (io.in.fire()) {
-    printf("%c", io.in.bits)
     shifter := Cat(io.in.bits, Bits(0, 1))
     counter := Mux1H((0 until uartStopBits).map(i =>
       (io.nstop === UInt(i)) -> UInt(n + i + 1)))