From: Cesar Strauss <cestrauss@gmail.com>
Date: Sun, 14 Apr 2024 18:51:43 +0000 (-0300)
Subject: ls2: add support for the Nexys Video board
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;p=ls2.git

ls2: add support for the Nexys Video board
---

diff --git a/src/ls2.py b/src/ls2.py
index f151cb4..48f6cca 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -58,6 +58,12 @@ from nmigen_boards.versa_ecp5 import VersaECP5Platform
 from nmigen_boards.versa_ecp5 import VersaECP5Platform85 # custom board
 from nmigen_boards.ulx3s import ULX3S_85F_Platform
 from nmigen_boards.arty_a7 import ArtyA7_100Platform
+# TODO: remove try..catch guards below when Nexys Video support is merged
+#       into nmigen-boards
+try:
+    from nmigen_boards.nexys_video import NexysVideoPlatform
+except ImportError:
+    NexysVideoPlatform = None
 from nmigen_boards.test.blinky import Blinky
 from nmigen_boards.orangecrab_r0_2 import OrangeCrabR0_2_85k_Platform
 from icarusversa import IcarusVersaPlatform
@@ -303,7 +309,7 @@ class DDR3SoC(SoC, Elaboratable):
             self.crg = ECP5CRG(clk_freq, dram_clk_freq=dram_clk_freq,
                                pod_bits=pod_bits, sync_bits=sync_bits,
                                need_bridge=need_bridge)
-        if fpga in ['arty_a7']:
+        if fpga in ['arty_a7', 'nexys_video']:
             self.crg = ArtyA7CRG(clk_freq)
 
         self.dram_clk_freq = dram_clk_freq
@@ -832,12 +838,14 @@ def build_platform(fpga, firmware):
                      'ulx3s': ULX3S_85F_Platform,
                      'orangecrab': OrangeCrabR0_2_85k_Platform,
                      'arty_a7': ArtyA7_100Platform,
+                     'nexys_video': NexysVideoPlatform,
                      'isim': IcarusVersaPlatform,
                      'orangecrab_isim': IcarusVersaPlatform,
                      'rcs_arctic_tern_bmc_card':None, #TODO
                      'sim': None,
                     }[fpga]
     toolchain = {'arty_a7': "yosys_nextpnr",
+                 'nexys_video': "yosys_nextpnr",
                  'versa_ecp5': 'Trellis',
                  'versa_ecp5_85': 'Trellis',
                  'orangecrab_isim': 'Trellis',
@@ -848,6 +856,7 @@ def build_platform(fpga, firmware):
                  'sim': None,
                 }.get(fpga, None)
     dram_cls = {'arty_a7': None,
+                 'nexys_video': None,
                  'versa_ecp5': MT41K64M16,
                  'versa_ecp5_85': MT41K64M16,
                  'orangecrab': MT41K64M16,
@@ -887,6 +896,8 @@ def build_platform(fpga, firmware):
         dram_clk_freq = 100e6
     if fpga == 'arty_a7':
         clk_freq = 27.0e6 # urrr "working" with the QSPI core (25 mhz does not)
+    if fpga == 'nexys_video':
+        clk_freq = 25.0e6
     if fpga == 'ulx3s':
         clk_freq = 40.0e6
     if fpga == 'orangecrab' or fpga=='orangecrab_isim':