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Wishbone debug module
[microwatt.git]
/
Makefile
2019-09-20
Benjamin Herrenschmidt
Wishbone debug module
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2019-09-20
Benjamin Herrenschmidt
Add a debug (DMI) bus and a JTAG interface to it on...
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2019-09-16
Anton Blanchard
Merge pull request #62 from antonblanchard/byte-reverse...
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2019-09-16
Anton Blanchard
Merge pull request #61 from antonblanchard/execute...
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2019-09-16
Anton Blanchard
execute1 no longer needs sim_console
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2019-09-15
Anton Blanchard
Merge pull request #60 from antonblanchard/testbenches
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2019-09-15
Anton Blanchard
Fix multiply_tb
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2019-09-15
Anton Blanchard
Add an icache testbench
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2019-09-12
Anton Blanchard
Merge pull request #49 from antonblanchard/icache-2
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2019-09-12
Anton Blanchard
Add a simple direct mapped icache
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2019-09-10
Anton Blanchard
Merge pull request #40 from antonblanchard/makefile...
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2019-09-10
Anton Blanchard
Update Makefile dependencies
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2019-09-10
Benjamin Herrenschmidt
Share soc.vhdl between FPGA and sim
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2019-09-09
Anton Blanchard
Merge pull request #33 from antonblanchard/cr-fix
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2019-09-09
Anton Blanchard
Merge pull request #32 from antonblanchard/register...
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2019-09-09
Benjamin Herrenschmidt
Use simulated UART in core test bench
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2019-09-08
Anton Blanchard
Merge pull request #20 from antonblanchard/reset-rework2
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2019-09-07
Anton Blanchard
Rework SOC reset
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2019-09-03
Anton Blanchard
Merge pull request #16 from antonblanchard/decode2_rework2
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2019-09-03
Anton Blanchard
Rework decode2
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2019-08-29
Anton Blanchard
Merge pull request #7 from riktw/fusesoc_arty_a7
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2019-08-28
Anton Blanchard
Merge pull request #5 from antonblanchard/travis-test
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2019-08-28
Anton Blanchard
Add an initial travis.yml
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2019-08-27
Anton Blanchard
Merge pull request #6 from mikey/gif
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2019-08-27
Anton Blanchard
Add -Wall to CFLAGS
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2019-08-22
Anton Blanchard
Initial import of microwatt
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