Renamed OpClass enum members: they all end in 'Op' now.
[gem5.git] / arch / isa_parser.py
2004-05-31 Steve ReinhardtRenamed OpClass enum members: they all end in 'Op'...
2004-05-28 Kevin LimUpdated FastCPU model with all the recent changes.
2004-05-28 Kevin LimMerged in new FastCPU stuff with existing code.
2004-05-27 Kevin LimFastCPU model added. It's very similar to the SimpleCP...
2004-05-20 Nathan BinkertMerge zizzer.eecs.umich.edu:/m5/Bitkeeper/m5
2004-05-19 Steve ReinhardtAdd a level of indirection to the register accessors...
2004-05-17 Steve ReinhardtMerge zizzer:/bk/m5 into isabel.reinhardt.house:/z...
2004-05-17 Steve ReinhardtMerge zizzer:/bk/m5 into isabel.reinhardt.house:/z...
2004-05-17 Steve ReinhardtSignificant changes to ISA description to completely...
2004-05-10 Steve ReinhardtDo a better job of factoring out CPU model in ISA descr...
2003-10-14 Nathan BinkertMerge
2003-10-14 Steve ReinhardtMerge zizzer:/bk/m5 into isabel.reinhardt.house:/z...
2003-10-14 Steve ReinhardtFix up decoder.cc generation... this got broken at...
2003-10-08 Steve ReinhardtFix attribution for decoder.cc.
2003-10-08 Steve ReinhardtMerge zizzer:/bk/m5 into isabel.reinhardt.house:/z...
2003-10-07 Nathan Binkertisa_parser.py:
2003-10-07 Steve RaaschImport changeset