Merge branch 'koriakin/xc7nocarrymux' into xaig
[yosys.git] / backends / blif /
2019-06-26 Eddie HungMerge branch 'xc7nocarrymux' of https://github.com...
2019-06-13 Serge BazanskiMerge pull request #829 from abdelrahmanhosny/master
2019-06-12 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-07 Clifford WolfMerge branch 'pr_elab_sys_tasks' of https://github...
2019-06-06 David ShahMerge pull request #1073 from whitequark/ecp5-diamond-iob
2019-06-05 Clifford WolfMerge pull request #999 from jakobwenzel/setundefInitFix
2019-05-31 Eddie HungMerge branch 'xaig' into xc7mux
2019-05-27 Stefan BiereigelMerge branch 'master' into wandwor
2019-05-27 Clifford WolfMerge pull request #1026 from YosysHQ/clifford/fix1023
2019-05-27 Clifford WolfMerge pull request #1030 from Kmanfi/makefile_osx
2019-05-26 Clifford WolfMerge pull request #1035 from YosysHQ/eddie/opt_rmdff
2019-05-26 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-05-25 Clifford WolfMerge pull request #1041 from YosysHQ/clifford/fix1040
2019-05-25 Clifford WolfFix handling of offset and upto module ports in write_b...
2019-04-30 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/xc7srl' into xc7mux
2019-04-22 Clifford WolfMerge pull request #905 from christian-krieg/feature...
2019-04-22 Clifford WolfMerge pull request #941 from Wren6991/sim_lib_io_clke
2019-04-22 Clifford WolfMerge branch 'master' of https://github.com/dh73/yosys_...
2019-04-22 Clifford WolfMerge pull request #911 from mmicko/gowin-nobram
2019-04-22 Clifford WolfMerge pull request #909 from zachjs/master
2019-04-22 Clifford WolfMerge pull request #944 from YosysHQ/clifford/pmux2shiftx
2019-04-21 Eddie HungMerge branch 'master' into map_cells_before_map_luts
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/clifford/pmux2shif...
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-20 Clifford WolfMerge pull request #943 from YosysHQ/clifford/whitebox
2019-04-18 Eddie HungMerge remote-tracking branch 'origin/clifford/whitebox...
2019-04-18 Clifford WolfAdd "whitebox" attribute, add "read_verilog -wb"
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2018-04-15 Clifford WolfAdd "write_blif -inames -iattr"
2017-05-17 Clifford WolfAdd $_ANDNOT_ and $_ORNOT_ gates
2016-11-23 Clifford WolfAdded wire start_offset and upto handling BLIF back-end
2016-10-19 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-10-18 Clifford WolfUse init value "2" for all uninitialized FFs in BLIF...
2016-10-11 Clifford WolfAdded $ff and $_FF_ cell types
2016-07-08 Clifford WolfMerge branch 'eddiehung-vtr'
2016-07-08 Clifford WolfRestored blif "-true - .." behavior, use "-true + ...
2016-07-08 Clifford WolfIn BLIF, a .names without entries already always outputs 0
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-06-19 Clifford WolfMerge branch 'sv_packages' of https://github.com/rubund...
2016-06-18 Clifford WolfAdded $sop support to BLIF back-end
2016-05-06 Clifford WolfAdded "write_blif -noalias"
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-22 Clifford WolfAdded support for "active high" and "active low" latche...
2016-04-21 Clifford WolfAdded "yosys -D" feature
2016-04-07 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-05 Clifford WolfFixed some typos
2016-01-06 Clifford WolfAdded "write_blif -cname" mode
2015-07-29 Clifford WolfImprovements in BLIF back-end
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-06-11 Clifford WolfFixed cstr_buf for std::string with small string optimi...
2015-05-24 Clifford WolfImprovements in BLIF front-end
2015-05-03 eddiehungFix for all zero mask
2015-05-03 eddiehungEscape '<' and '>' some more
2015-04-28 eddiehungFor vtr, escape angle brackets as well
2015-04-28 eddiehungblifwriter: write out .names for true/false/undef type...
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-03-02 Clifford WolfAdded write_blif -attr
2014-12-19 Clifford WolfFixed another bug in write_blif handling of $lut cells
2014-12-17 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-12-17 Clifford WolfFixed writing of $lut cells in BLIF backend
2014-12-14 Clifford WolfAdded "write_blif -undef" and support for special ...
2014-12-14 Clifford WolfAdded "write_blif -blackbox"
2014-12-14 Clifford WolfAdded "blif -unbuf" feature
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-09-06 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-09-06 Clifford WolfMerge pull request #38 from rubund/master
2014-09-06 Ruben UndheimCorrected spelling mistakes found by lintian
2014-08-23 Clifford WolfChanged backend-api from FILE to std::ostream
2014-08-15 Clifford WolfRenamed $lut ports to follow A-Y naming scheme
2014-08-15 Clifford WolfRenamed $_INV_ cell type to $_NOT_
2014-08-02 Clifford WolfNo implicit conversion from IdString to anything else
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize()
2014-07-23 Clifford WolfMerge branch: Refactoring {SigSpec|SigChunk}(RTLIL...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-02-22 Clifford WolfAdded $lut support to blif backend (by user eddiehung...
2014-02-21 Clifford WolfRenamed "write_blif -subckt" to "write_blif -icells...
2013-11-24 Clifford WolfAdded "top" attribute to mark top module in hierarchy
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