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Merge pull request #875 from YosysHQ/clifford/mutate
[yosys.git]
/
backends
/
btor
/
btor.cc
2019-01-02
Clifford Wolf
Merge pull request #755 from Icenowy/anlogic-dram-init
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2019-01-02
Clifford Wolf
Merge pull request #750 from Icenowy/anlogic-ff-init
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2018-12-31
Clifford Wolf
Merge pull request #766 from Icenowy/anlogic-latches
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2018-12-23
Clifford Wolf
Merge pull request #761 from whitequark/proc_clean_partial
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2018-12-23
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys
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2018-12-22
Clifford Wolf
Merge pull request #757 from whitequark/manual_mem
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2018-12-19
Clifford Wolf
Merge pull request #752 from Icenowy/anlogic-lut-cost
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2018-12-19
Clifford Wolf
Merge pull request #753 from Icenowy/anlogic-makefile-fix
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2018-12-19
Clifford Wolf
Merge pull request #749 from Icenowy/anlogic-dram-fix
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2018-12-18
Clifford Wolf
Minor style fixes
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2018-12-18
Clifford Wolf
Merge pull request #748 from makaimann/add-btor-ops
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2018-12-17
makaimann
Add btor ops for $mul, $div, $mod and $concat
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2018-12-16
Clifford Wolf
Merge pull request #736 from whitequark/select_assert_list
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2018-12-16
Clifford Wolf
Merge pull request #704 from webhat/feature/fix-awk
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2018-12-16
Clifford Wolf
Merge pull request #724 from whitequark/equiv_opt
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2018-12-16
Clifford Wolf
Merge pull request #729 from whitequark/write_verilog_i...
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2018-12-16
Clifford Wolf
Merge pull request #725 from olofk/ram4k-init
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2018-12-16
Clifford Wolf
Merge pull request #714 from daveshah1/abc_preserve_naming
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2018-12-16
Clifford Wolf
Merge pull request #723 from whitequark/synth_ice40_map...
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2018-12-16
Clifford Wolf
Merge pull request #722 from whitequark/rename_src
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2018-12-16
Clifford Wolf
Merge pull request #720 from whitequark/master
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2018-12-08
Clifford Wolf
Fix btor init value handling
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
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2017-12-24
Clifford Wolf
Add "no driver for signal bit" error msg to btor back-end
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2017-12-17
Clifford Wolf
Simple fix BTOR memory encoding
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2017-12-17
Clifford Wolf
Improve BTOR memory encoding
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2017-12-15
Clifford Wolf
Merge branch 'btor-ng'
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2017-12-15
Clifford Wolf
Add array support to btor back-end
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2017-12-14
Clifford Wolf
Add $anyconst/$anyseq support to btor back-end
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2017-12-14
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-12-14
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-12-12
Clifford Wolf
Add "write_btor -s" mode
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2017-12-12
Clifford Wolf
Add state initval handling to btor back-end
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2017-12-12
Clifford Wolf
Add btor back-end support for 'x' constants
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2017-12-11
Clifford Wolf
Add btor $shift/$shiftx support
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2017-12-10
Clifford Wolf
Fix btor back-end shift handling
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2017-12-10
Clifford Wolf
Add support for $pmux in btor back-end
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2017-12-10
Clifford Wolf
Add support for more cell types to btor back-end
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2017-12-10
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-12-09
Clifford Wolf
Fix btor concat
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2017-12-09
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-12-01
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-11-27
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-11-24
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-11-24
Clifford Wolf
Bugfixes in new BTOR back-end
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2017-11-23
Clifford Wolf
Progress in new BTOR back-end
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2017-11-23
Clifford Wolf
Progress in new BTOR back-end
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2017-11-23
Clifford Wolf
Progress in new BTOR back-end
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2017-11-23
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-11-23
Clifford Wolf
Progress with new BTOR backend
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2017-11-23
Clifford Wolf
Add skeleton for new BTOR back-end
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2017-11-23
Clifford Wolf
Remove old BTOR back-end
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-21
Clifford Wolf
Added "yosys -D" feature
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2016-02-13
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-02-13
Clifford Wolf
Added "int ceil_log2(int)" function
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2015-08-14
Clifford Wolf
Spell check (by Larry Doolittle)
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2015-08-05
Clifford Wolf
Remove some very strange whitespace in btor.cc (by...
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-06-11
Clifford Wolf
Fixed cstr_buf for std::string with small string optimi...
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2015-04-04
Clifford Wolf
Merge pull request #55 from ahmedirfan1983/master
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2015-04-03
Ahmed Irfan
separated memory next from write cell
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2015-01-24
Clifford Wolf
Added ENABLE_NDEBUG makefile options
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Clifford Wolf
Merge pull request #39 from ahmedirfan1983/master
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-09-18
ahmedirfan1983
fixed memory next issue, when same memory is written...
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2014-09-02
Ahmed Irfan
added $pmux cell translation
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2014-09-01
Clifford Wolf
Using std::vector<RTLIL::State> instead of RTLIL::Const...
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2014-08-23
Clifford Wolf
Changed backend-api from FILE to std::ostream
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2014-08-02
Clifford Wolf
No implicit conversion from IdString to anything else
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2014-08-02
Clifford Wolf
More cleanups related to RTLIL::IdString usage
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2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
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2014-07-29
Clifford Wolf
Added $shift and $shiftx cell types (needed for correct...
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2014-07-28
Clifford Wolf
Using log_assert() instead of assert()
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-26
Clifford Wolf
More RTLIL::Cell API usage cleanups
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Manual fixes for new cell connections API
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-25
Clifford Wolf
Various RTLIL::SigSpec related code cleanups
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2014-07-22
Clifford Wolf
SigSpec refactoring: change RTLIL::SigSpec::chunks...
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2014-03-07
Clifford Wolf
Use log_abort() and log_assert() in BTOR backend
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2014-02-13
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-12
Clifford Wolf
Merge pull request #26 from ahmedirfan1983/btor
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2014-02-11
Ahmed Irfan
register output corrected
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2014-02-11
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-02-11
Ahmed Irfan
added concat and slice cell translation
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