Try way that doesn't involve creating a new wire
[yosys.git] / backends / btor / test_cells.sh
2019-02-11 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init
2018-12-31 Clifford WolfMerge pull request #766 from Icenowy/anlogic-latches
2018-12-23 Clifford WolfMerge pull request #761 from whitequark/proc_clean_partial
2018-12-23 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2018-12-22 Clifford WolfMerge pull request #757 from whitequark/manual_mem
2018-12-19 Clifford WolfMerge pull request #752 from Icenowy/anlogic-lut-cost
2018-12-19 Clifford WolfMerge pull request #753 from Icenowy/anlogic-makefile-fix
2018-12-19 Clifford WolfMerge pull request #749 from Icenowy/anlogic-dram-fix
2018-12-18 Jim LawsonMerge remote-tracking branch 'upstream/master'
2018-12-18 Clifford WolfMinor style fixes
2018-12-18 Clifford WolfMerge pull request #748 from makaimann/add-btor-ops
2018-12-17 makaimannAdd btor ops for $mul, $div, $mod and $concat
2017-12-15 Clifford WolfMerge branch 'btor-ng'
2017-12-14 Clifford WolfMerge branch 'master' into btor-ng
2017-12-14 Clifford WolfMerge branch 'master' into btor-ng
2017-12-11 Clifford WolfAdd btor $shift/$shiftx support
2017-12-10 Clifford WolfFix btor back-end shift handling
2017-12-10 Clifford WolfAdd support for more cell types to btor back-end