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Fix "write_xaiger", and to write each box contents into holes
[yosys.git]
/
backends
/
edif
/
runtest.py
2017-03-19
Clifford Wolf
Add generation of logic cells to EDIF back-end runtest.py
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2017-03-19
Clifford Wolf
Fix EDIF: portRef member 0 is always the MSB bit
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2017-03-18
Clifford Wolf
Add simple EDIF test case generator and checker
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projects / yosys.git / history