Merge pull request #852 from ucb-bar/firrtlfixes
[yosys.git] / backends / edif /
2019-03-01 Clifford WolfFix "write_edif -gndvccy"
2019-02-17 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-01-17 Clifford WolfAdd "write_edif -gndvccy"
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-17 Clifford WolfMerge pull request #663 from aman-goel/master
2018-10-17 Clifford WolfMerge pull request #658 from daveshah1/ecp5_bram
2018-10-17 Clifford WolfMerge pull request #638 from udif/pr_reg_wire_error
2018-10-16 Clifford WolfMerge branch 'yosys-0.8-rc'
2018-10-13 tklamMerge branch 'master' of https://github.com/YosysHQ...
2018-10-05 Clifford WolfMerge pull request #651 from ARandomOWL/stdcells_fix
2018-10-05 Clifford WolfAdd "write_edif -attrprop"
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2017-07-11 Clifford WolfFix the fixed handling of x-bits in EDIF back-end
2017-07-11 Clifford WolfFix handling of x-bits in EDIF back-end
2017-03-19 Clifford WolfAdd generation of logic cells to EDIF back-end runtest.py
2017-03-19 Clifford WolfFix EDIF: portRef member 0 is always the MSB bit
2017-03-18 Clifford WolfAdd simple EDIF test case generator and checker
2017-02-25 Clifford WolfMerge branch 'klammerj-master'
2017-02-25 Clifford WolfImprove "write_edif" help message
2017-02-25 Clifford WolfMove EdifNames out of double-private namespace
2017-02-25 Clifford WolfClean up edif code, swap bit indexing of "upto" ports
2017-02-25 Clifford WolfMerge branch 'master' of https://github.com/klammerj...
2017-02-24 Johann KlammerDid as you requested, /but/...
2017-02-23 Johann Klammeradd options for edif flavors
2017-02-14 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-14 Clifford WolfAdd warning about x/z bits left unconnected in EDIF...
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2016-04-07 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-05 Clifford WolfFixed some typos
2016-03-11 Clifford WolfMerge commit 'b34385ec924b6067c1f82bdbae923f8062518956'
2016-03-08 Clifford WolfAdded "write_edif -nogndvcc"
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-01 Clifford WolfAdded EDIF backend support for multi-bit cell ports
2014-10-10 Clifford WolfRenamed SIZE() to GetSize() because of name collision...
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-08-23 Clifford WolfChanged backend-api from FILE to std::ostream
2014-08-02 Clifford WolfNo implicit conversion from IdString to anything else
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize()
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::expand() method
2014-07-23 Clifford WolfMerge branch: Refactoring {SigSpec|SigChunk}(RTLIL...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-02-21 Clifford WolfBetter handling of nameDef and nameRef in edif backend
2014-02-21 Clifford WolfFixed instantiating multi-bit ports in edif backend
2013-12-04 Clifford WolfReplaced RTLIL::Const::str with generic decoder method
2013-11-24 Clifford WolfAdded "top" attribute to mark top module in hierarchy
2013-11-22 Clifford WolfRenamed "placeholder" to "blackbox"
2013-11-04 Clifford WolfImproved comments on topological sort in edif backend
2013-11-03 Clifford WolfAdded simple topological sort to edif backend
2013-11-03 Clifford WolfWrite yosys version to output files
2013-10-27 Clifford WolfFixed hex string generation bug in edif backend
2013-10-24 Clifford WolfFixed handling of boolean attributes (backends)
2013-09-17 Clifford WolfImprovements in EDIF backend
2013-09-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-08-28 Clifford WolfEncode large (>32 bits) parameters as hex string in...
2013-08-27 Clifford WolfImproved edif backend
2013-08-22 Clifford WolfAdded correct encoding of identifiers in EDIF backend
2013-08-22 Clifford WolfAdded edif backend (still under construction)